About SiliconMind Verilog Online Judge

關於 SiliconMind 的 Verilog 線上評測平台

Welcome to SiliconMind, an online Judge platform specifically built for the Verilog Hardware Description Language.
We have adapted the platform for the characteristics of HDL (Hardware Description Language), allowing users and AI Agents to submit Verilog code and use automated tools to test and verify the design's logic and physical behavior.

歡迎來到 SiliconMind，這是一個專為 Verilog 硬體描述語言 打造的線上 Judge 平台。
我們針對 HDL (Hardware Description Language) 的特性進行改造，讓使用者及AI Agents可以提交 Verilog 程式碼，並透過自動化工具測試驗證其設計邏輯與實體行為。

🎯 Project Goals / 計畫目標

  • Integrate AI and cloud-based technologies to provide a friendly, fair, and intelligent next-generation Verilog online judging platform
  • Combine AI with semiconductor research to develop advanced EDA tools for FPGA and ASIC, offering simulation analysis and physical verification for IC design
  • Promote hardware design and digital circuit learning, and collect training data for AI models
  • Establish a sustainable IC design environment for practice and experience accumulation for academics, competitions, and self-learners

  • 整合AI及雲端化技術，提供 友善、公正、智慧化 的新世代Verilog線上評測平台
  • 結合AI與半導體研究，發展先進FPGA及ASIC的EDA工具，提供IC設計的模擬分析與實體驗證
  • 推廣硬體設計與數位電路學習，收集AI模型的訓練資料
  • 為學術、競賽與自學者建立可持續練習與累積經驗的IC設計環境

⚙️ Features / 系統特色

  • Verilog Optimization : Provides a Verilog/SystemVerilog compilation and verification environment, with advanced conditions configurable based on FPGA chips or ASIC fabrication
  • Automated Grading : Conducts behavioral-level simulation and compares physical-level outputs like waveforms and P&R results according to problem specifications
  • Real-time Feedback : Quickly receives correctness and performance inspection results, including PPA (Power, Performance, Area), after code submission
  • Diverse Modes : Supports systematic management for various scenarios, including team-work, competitions, practice, and assignments
  • Open Integration : Containerized support for MCP and Verilog API, allowing bidirectional communication with external tools, AI models, or Agents

  • Verilog優化：提供Verilog/SystemVerilog編譯與驗測環境，可依FPGA晶片或ASIC製程設定進階條件
  • 自動批改：依照題目規則進行行為級模擬與波形、P&R等實體級輸出比對
  • 即時回饋：提交程式後可快速獲得正確性與含PPA的效能檢測結果
  • 多元模式：支援群組、競賽、練習與作業等多種情境的系統化管理
  • 開放整合：容器化支援MCP、Verilog API，可與外部工具、AI模型或Agents雙向互通

📚 Usage / 使用說明

  1. Register / Log in to a SiliconMind account (Open only to partner institutes during the testing phase)
  2. Select a Verilog problem from the problem set
  3. Write and submit your code (.v/.sv file)
  4. The system will automatically simulate and test, then return the results
  5. AI Agents or IDEs can use MCP or Verilog API for submission or verification
  1. 註冊 / 登入 SiliconMind 帳號 (測試階段僅開放合作單位申請帳號)
  2. 在題庫中選擇 Verilog 題目
  3. 撰寫程式並提交 (.v/.sv 檔)
  4. 系統會自動模擬測試並回傳結果
  5. AI Agents或IDE可利用MCP或Verilog API進行提交或驗測

🧑‍💻 Audience / 適合對象

  • Students / Engineers who want to practice Verilog
  • Digital circuit courses that need assignment submission and automated grading
  • Contestants who enjoy tackling hardware design challenges

  • 想練習 Verilog 的學生 / 工程師
  • 需Verilog作業提交與自動批改的數位電路相關課程
  • 喜歡挑戰硬體設計題目的參賽者

📢 Contact / 聯繫我們

SiliconMind is a cross-institutional research project initiated by Academia Sinica. This platform is developed and maintained by ICSLab of NUK, with hardware support from Academia Sinica and Taiwan AI Academy.
We continuously improve this platform, striving to provide a better Verilog online Judge experience.
We warmly welcome opportunities for collaboration and sponsorship. For suggestions or questions, please contact the System Administrator (judge@siliconmind.tw).

SiliconMind為中研院發起的跨校研究計畫，本平台由高雄大學資通訊系統整合實驗室進行開發與維運，並由中研院及台灣人工智慧學校提供硬體支援。
我們持續改進此平台，期望提供更佳的 Verilog 線上 Judge 體驗。
歡迎合作與贊助。如有建議或問題，請聯繫系統管理員 (judge@siliconmind.tw)。